This invention relates to a CDMA receiver for direct sequence spread spectrum communications (hereafter xe2x80x9cDSxe2x80x9d), and more particularly to a CDMA receiver which can be synchronized with a reference timing.
Development of digital cellular wireless communication systems employing DS-CDMA (direct sequence code division multiple access) technology is being developed as a next-generation mobile communication system to achieve wireless multimedia communication. In this CDMA communication, a plurality of channels or information for transmission by the user is multiplexed by means of spreading codes, and is transmitted via wireless circuits or other transmission routes.
In mobile communications, random changes in amplitude and phase known as fading occur, having a maximum frequency determined by the velocity of the mobile object and the carrier wave frequency. Because of this, stable reception is extremely difficult compared with fixed wireless communication. Spread spectrum communication methods are effective as a means of reducing the degradation caused by the effects of such frequency-selective fading. Because signals in a narrow band are spread over a high-frequency band for transmission, even if a drop in received electric field intensity occurs in a specific frequency region, information can be restored without errors from other bands.
Further, when in mobile communications fading similar to that described above occurs due to the environment in the vicinity of the receiver caused by delayed waves resulting from distant tall buildings, mountains and similar, a multi-path fading environment results. When using DS, these delayed waves become interference waves with respect to spreading codes, and so induce degradation of reception characteristics. The RAKE reception method is known as one method which can be used to effectively improve characteristics with respect to these delayed waves. In this method, despreading is performed for each delayed wave arriving via each of the multiple paths, the respective delay times are arranged, and combining is performed by weighting according to the reception level and adding.
FIG. 23 is an example of the configuration of a CDMA wireless device of the prior art; 1 is the transmission circuit, 2 is the reception circuit, 3 is a duplexer which sends transmission signals to the antenna and inputs reception signals to the reception circuit, and 4 is the antenna. In the transmission circuit 1, 1a is an encoder which encodes transmission signals (transmission data), and 1b is a mapping unit; for example, frame data (pilot signal and transmission data) is divided, alternating for each bit, into two series, I symbol data DI, which is the same-phase component (I or in-phase component), and Q symbol data DQ, which is the orthogonal component (Q or quadrature component). 1c and 1d are spreaders which perform spreading modulation on the I symbol data and Q symbol data DI, DQ using prescribed spreading codes; 1e and 1f are waveform-shaping filters; 1g and 1h are D/A converters which perform D/A conversion of the output of the filters 1e, if; 1i is a quadrature modulation circuit which executes QPSK quadrature modulation of the I channel signal and Q channel signal and outputs the results; and 1j is a wireless unit which performs frequency conversion from IF to RF, high-frequency amplification, and other operations.
In the reception circuit 2, 2a is a wireless unit which performs frequency conversion from RF to IF, high-frequency amplification, and other operations; 2b is a quadrature detection circuit which uses orthogonal detection to demodulate the I channel and Q channel signals; 2c and 2d are A/D converters which convert the I channel and Q channel signals into digital data; 2e is a path search circuit which searches for multiple paths; 2f is a RAKE combining/demodulation unit which executes despreading for each of multiple paths, demodulates the the I symbol data DIxe2x80x2 and Q symbol data DQxe2x80x2 obtained by despreading into the original data, and combines and outputs the demodulation results; and 2g is a decoder.
FIG. 24 is a schematic diagram of the path search unit 2e and RAKE combining/demodulation unit 2f. The RAKE combining/demodulation unit 2f has finger units 51, 52, 53 provided for each path of multiple paths, and a RAKE combining unit 6 which combines the outputs of the finger units. The path search unit 2e comprises a matched filter (MF) 7a, an integration circuit 7b, a path selection section 7c, and a timing generation section 7d; multiple paths are detected, the time delays from the arrival times of signals arriving via each path among multiple paths, or from a reference time, are discriminated, and the timing data P1 to P3 for start of despreading for the finger units corresponding to each path, and time delay adjustment data D1 to D3, are input.
The reception level for signals sent from a transmitter vary according to the path among multiple paths as shown in FIG. 25, and also differ for different times of arrival at the receiver. The matched filter 7a outputs the auto-correlation of the desired signal contained in the reception signal. Because channel components other than the channel allocated to a matched filter 7a are also contained in the reception output of the antenna 4, the matched filter 7a uses the spreading code for its own channel to extract the signal component for its own channel (the desired signal) from the antenna reception signal, and outputs the result. In this case, the correlation values I, Q of the I channel signal and the Q channel signal are obtained independently, so that for example the calculation (I+jQ) (Ixe2x88x92jQ)=I2+Q2 is performed to convert to a power value, which is output.
That is, when direct-sequence signals (DS signals) which have been affected by multiple paths enter the matched filter 7a, a pulse train is output which has a plurality of peaks corresponding to the arrival time delay and the received electric field intensity; after passing through the integration circuit 7b, this pulse train enters the path selection section 7c. In order to remedy the loss due to instantaneous level drops caused by fading, the integration circuit 7b takes a time average of the matched filter output, and inputs the result to the path selection section 7c. The path selection section 7c refers to the integration output (FIG. 25) of the integration circuit, detects multiple paths based on the multiple path signals MP1, MP2, MP3 which are greater than a threshold value, detects each of the paths of the multiple paths and the time delays t1, t2, t3, and inputs, to the finger units 51, 52, 53 corresponding to each path, the timing data for start of despreading P1, P2, P3 and the time delay adjustment data D1, D2, D3. The multipath signals MP1, MP2, MP3 are arranged in order of magnitude, and the path with the largest multipath signal is allocated to the first finger 51, while the path with the second-largest multipath signal is allocated to the second finger 52, and the path with the third-largest multipath signal is allocated to the third finger 53; the processing described below is then performed on signals arriving via the paths assigned to each of these finger units.
The finger units 51, 52, 53 corresponding to the paths have the same configuration, each having a despreading circuit 5a, demodulation circuit 5b, and delay circuit 5c. Each of the despreading circuits 5a uses the spreading code for its own channel to perform despreading processing of the received I channel signal and Q channel signal, with timing (P1 to P3) indicated by the path search unit 2e. The demodulation circuit 5b uses the I symbol data DIxe2x80x2 and Q symbol data DQxe2x80x2, obtained from despreading, to demodulate to obtain the original data; the delay circuit 5c outputs this data with a delay (D1 to D3) indicated by the path search unit 2e. As a result, each of the finger units performs despreading with the same timing as the spreading codes of the transmitter, and adjusts the time delays according to the path, arranges the phases and inputs the signals to the RAKE combining unit 6; the RAKE combining unit 6 combines the input signals for output.
FIG. 26 shows an example of the configuration of the despreading circuit in a finger unit; despreading processing is performed on the I channel signals and on the Q channel signals. 8a is a spreading code generator unit which generates the same spreading codes as the transmitter; the code length is the number of chips per symbol N, for example, 256. 8b is a multiplier which multiplies the I channel signal and the spreading code for each chip; 8bxe2x80x2 is a multiplier which multiplies the Q channel signal and the spreading code for each chip; 8c and 8cxe2x80x2 are integrators which integrate the multiplication result over one symbol period (256 cumulative additions); 8d and 8dxe2x80x2 are adders; 8e and 8exe2x80x2 are one-chip time delay circuits; and 8f and 8fxe2x80x2 are output registers which use the symbol clock to latch the one-symbol period cumulative result and output the I symbol data DIxe2x80x2, DQxe2x80x2.
To summarize the above, in the matched filter 7a of the path search unit 2e, the correlation between the received signal and the desired signal (the expected spreading code train) is determined, the path for which this correlation is large is selected by the path selection section 7c, and the despreading circuit 5a is notified of the time difference. In FIG. 24, despreading is performed for three paths with large integration outputs of correlations.
The arrival times t1, t2, t3 of three apparently certain paths detected in this way are taken to be the despreading timing of the despreading circuits 5a in the respective finger units 51, 52, 53. In each of the despreading circuits 5a, despreading codes are generated according to the despreading timing obtained in this way, and despreading of received data is performed. If there is phase modulation, the oritinal data is restored from the I, Q symbol data obtained by despreading by means of the demodulation circuit 5b. Then, the positions of the restored data are aligned by using the delay circuits 5c to shift the two faster signals to agree with the slowest signal, based on the respective delay amounts. By adding these, a combined signal is obtained. This result is subjected to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d judgment by the comparator of a data judgment unit, not shown, and the result is taken to be the received data. In some cases, maximal ratio combining is performed by multiplying by a reliability corresponding to the respective reception levels and then adding, prior to combining by the RAKE combining unit 6.
In the above explanation, no DLL (delay locked loop) circuit is provided; but in actuality, as shown in FIG. 27, DLL circuits 91 to 93 are provided between the path search unit 2e and each of the finger units 51, 52, 53. Even if the path search unit 2e acquires the synchronization, if nothing further is done, fluctuations in the system clock frequency, changes in distance between transmitter and receiver, the effects of noise and other factors will cause the synchronization position to be lost. Hence when acquisition of synchronization using the correlator 7axe2x80x2 is successful, control must be exercised such that despreading code trains on the receiving side are not shifted in time (synchronization tracking). The DLL circuits 91 to 93 exercise control such that the despreading timing in the finger units 51 to 53 is synchronized with the timing indicated by the initial timing data generation section 7d of the path search unit 2e. 
FIG. 28 is a schematic diagram of the DLL circuit. 9a is a despreading code generator which cyclically generates a despreading code train A1 for N chips in each symbol interval; initial values are loaded according to timing data output from the initial timing generator 7d. 9b is a delay circuit which delays the despreading code train A1 by one chip period and outputs a second despreading code train A2; 9c and 9d are multipliers which multiply the despreading codes A1, A2 by a carrier signal; 9e is a multiplier which multiplies the first despreading code train A1 and the received signal (received spreading code train) B for each chip; 9f is a multiplier which multiplies the second despreading code train A2, delayed by one chip, and the received spreading code train B for each chip; 9g and 9h are band-pass filters; 9i and 9j are envelope detectors; 9k is an adder which adds the output of the envelope detector 9i and the inversion of the code of the output of the envelope detector 9j; 9m is a low-pass filter; 9n is a voltage-controlled oscillator (VCO) with clock frequency (chipping rate) variable based on the low-pass filter output; and 9p is a counter which counts the chip clock and outputs a despreading timing signal.
The multiplier 9e has a function for calculating the correlation between the despreading code train A1 and the received spreading code train B; the correlation is maximum if these codes are in phase. Hence the envelope detector 9i outputs the correlation R(xcfx84)=1 for one chip period for each symbol, as shown in FIG. 29A, and if the phase is shifted by one chip period or more outputs the correlation R(xcfx84)=1/N. The multiplier 9f has a function for calculating the correlation between the second despreading code train A2 and the received spreading code train B; the correlation is maximum if these codes are in phase. Hence the envelope detector 9j outputs the correlation R(xcfx84)=1 for one chip period for each symbol, as shown in FIG. 29B, and if the phase is shifted by one chip period or more outputs the correlation R(xcfx84)=1/N. The adder 9k adds the inversion of the code of the output of the envelope detector 9i and the output of the envelope detector 9j, and by this means outputs via the low-pass filter 93 a signal having the S-curve characteristic with respect to phase difference xcfx84 shown in FIG. 29C.
The voltage-control oscillator 9g controls the clock frequency, based on the low-pass filter output, such that the phase difference xcfx84 becomes 0. For example, if the phase of the despreading code advances relative to the received spreading code, the clock frequency is lowered and controlled such that the phase difference becomes 0; or, if the phase of the despreading code lags relative to the received spreading code, the clock frequency is raised and controlled such that the phase difference becomes 0.
As explained above, the phase of the transmission-side spreading code train (received spreading code train) is detected with a precision of within one chip by the path search unit 2e (synchronization acquisition), and then synchronization tracking is performed by the DLL circuits 91 to 93, and the despreading code train A1 synchronized with the phase of the transmission-side spreading code train is input to the finger units.
In mobile communications, the environment of either the transmitter or the receiver, or both, changes with time, and so the path search unit 2e must infer, from changes in the delay amounts and reception levels, that the three newly detected paths are the same as the three paths received until that time, and the RAKE receiver must use the signals from the three paths to control RAKE reception. Further, a new path with different delay may appear to be more certain than the three paths (with large reception intensities) which had initially appeared certain. In this case, path allocations must be switched. In the path allocation switching of the prior art, the multiple path signals are arranged in order of magnitude, the path with the largest multipath signal is allocated to the first finger unit 51, the path with the second-largest multipath signal is allocated to the second finger unit 52, and the path with the third-largest multipath signal is allocated to the third finger unit 53. However, in this allocation method, if the delay of the path newly inferred to be certain is small, part of the spreading period sent via the other two paths is lost.
FIG. 30 is a diagram explaining loss of data which arises upon switching path allocations. Upon the first switching of path allocations, the correlations of five paths, a to e, obtained from the matched filter 7a have magnitudes in the order b greater than d greater than e greater than a greater than c. The path selection section 7c selects the upper three paths b, d, e, allocating path b to the first finger unit 51, path d to the second finger unit 52, and path e to the third finger unit 53. The finger units 51, 52, 53 execute despreading on signals arriving from the paths b, d, e at respective times T11, T12, T13, delays the obtained despreading signals by time delays d1, d2, d3 to arrange the phases, and outputs the signals.
Next, on the second switching of path allocations, the magnitudes of the correlations of the five paths a to e obtained from the matched filter 7a are in the order d greater than b greater than a  greater than e greater than c. The path selection section 7c selects the upper three paths d, b, a, and assigns path d to the first finger unit 51, the path b to the second finger unit 52, and path a to the third finger unit 53. As a result, the finger units 51, 52, 53 execute despreading on signals incoming from the paths d, b, a at respective times T21, T22, T23; the despreading signals obtained are delayed by time delays d1xe2x80x2, d2xe2x80x2, d3xe2x80x2 to arrange phases, and are output. By means of the above, if there are eight symbols of valid data received via path b between the first and second path switching times, then there are 6.7 symbols of valid data received via path d, and 4.6 symbols of valid data received via path e. Consequently 1.3 symbols"" worth of data is lost from path d (lost portion DF1), and 3.4 symbols"" worth of data is lost from path e (lost portion DF2), compared with the maximum length of valid data (8 symbols). In these lost portions the spreading gain is reduced, and detection accuracy is degraded.
Even in cases where the three apparently certain paths do not change, if the multipath signal level (correlation) changes, path allocation switching is performed, and the above-described data losses occur. Also, depending on the reception environment and the symbol period, still more symbols may be lost, and in some cases data from all paths may be lost.
In the above path search method, finger units are allocated beginning from paths with higher reception levels. This path allocation method has the advantage of being simply executable. However, the above-described data losses occur, and moreover, even for the same three paths, depending on the multipath signal level (correlation), mutual substitution may be performed, and data losses may arise due to this substitution.
In light of the above, it is necessary that the identity of the previous paths and the present paths be accurately judged, and that, in cases where they are the same, that the allocation of finger units to these paths not be changed.
The transmission/reception clock of the base station and mobile equipment sweeps asynchronously, and there are fluctuations in the system clock of the mobile equipment. Consequently some kind of timing synchronization is needed, in order to synchronize the timing of the mobile equipment with the reference timing of the base station. Conventionally, this timing control is performed by a DLL circuit; but a DLL circuit is necessary for each path (finger), and there is the further problem that a VCO, envelope detector, various filters, and other analog circuitry is also required.
Hence an object of this invention is to accurately judge whether paths are identical, and if paths are identical, to prevent changes in the allocation of paths to fingers.
Another object of this invention is to perform synchronization to the reference timing, without using DLL circuits.
Still another object of this invention is to provide a CDMA receiver having a path follow-up function which is digitally equivalent to a DLL circuit.
The path search unit in a CDMA receiver comprises (1) a correlation detection section, which detects the correlation, in each prescribed time interval, between a received signal and a desired signal; (2) a path selection section, which selects a plurality of paths along which the desired signal arrives based on the peak level of the above correlation, and employs the peak detection time as the desired signal detection time; (3) a path judgment section, which, if the difference between the detection time of the desired signal arriving via a path selected this time and the previous detection time is within an allowable range, judges that the path selected this time is identical to the path previously allocated to the prescribed despreading/delay adjustment section; and (4) a path allocation section which performs path allocation, such that, if the path selected this time is identical to the previously allocated path, despreading and delay adjustment processing are performed for the desired signal arriving via the selected path by the same despreading/delay adjustment section as previously. The timing control unit comprises (1) a calculating section, which calculates the difference between the desired signal detection time this time for the above identical path and reference time, and (2) a timing control circuit, which controls the lead or lag in the timing based on the sum of the above time differences in each identical path.
By configuring the CDMA receiver in this way, if the paths already allocated to finger units (despreading/delay adjustment units) and the paths selected this time are the same, the allocation of paths to finger units is not changed, and so data loss at the time of path allocation can be prevented.
Because judgment of whether paths are identical is made depending on whether differences in detection times are within an allowable range for example time interval for one chip, the precision of estimation of path identity can be raised.
The phase of the transmission-side spreading code train can be detected by the path search unit with a precision within one chip (synchronization acquisition), and the lead/lag of the timing signal can be controlled based on the sum of differences for the detection time this time and the reference time for each identical path (synchronization tracking). As a result, even if there are fluctuations in the distance between transmitter and receiver or in the system clock, the timing of each unit can be synchronized with the reference timing of the base station, and DLL circuits can be made unnecessary. Moreover, (1) when a new path is allocated to each finger unit, the desired signal detection time for the path is taken to be the reference time; or, (2) the base station frame start time detected at the start of communication with the base station is taken to be the reference time.
The timing control circuit controls the timing lead and lag as follows.
In a first method, according to whether the detection time this time is later than or earlier than the reference time, the above time difference is changed by +1 or xe2x88x921, to control the timing lead or lag based on the sum of time differences for each identical path. By this means, the hardware configuration can be made simple.
In a second method, time differences are weighted based on the magnitude of the correlation (reception level)at this time, and the timing lead or lag is controlled based on the sum of weighted time differences for each identical path. In this way, paths with high correlations can be endowed with high reliability in controlling the timing (synchronization tracking control).
In a third method, the number of paths judged to be identical paths is detected, the sum of time differences is normalized based on the number of paths, and the lead or lag of the timing is controlled based on the value obtained. By this means, timing control (synchronization tracking control) can be performed with constant sensitivity even if there are changes in the number of paths due to the electromagnetic wave environment.
In a fourth method, the sum of time differences is normalized based on the number of paths which are judged to be the same paths as the previous time, and the correlations of which are equal to or greater than a prescribed level; the timing lead or lag is controlled based on the value obtained. By this means, the electromagnetic wave environment can be further taken into account in performing timing control (synchronization tracking control) with constant sensitivity.
Specific methods of timing control are as follows. (1) control the voltage-controlled oscillator (VCO) based on the sum of time differences, in order to control the frequency of the system clock. (2) When the pulse output from a fast clock oscillator is frequency-divided to generate the system clock, pulses are inserted or removed based on the sum of time differences, to control the system clock frequency. (3) When the system clock is frequency-divided and various timing signals are generated, the frequency division ratio is controlled based on the sum of time differences in order to control the lead or lag of the timing.